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There are currently no product reviews.
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Excellent quality. Easy process to download. No issues or problems at all - was exactly what I was looking for and needed. Great service.
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I was having a hard time finding the problem with this Mackie 1604 unit. I didn't have a schematic. Went looking on the web and found your site and the price was more then reasonable. Ordered it and within the hour had the manual and within 15 minutes had the unit fixed. Best $4.99 I ever spent. Thank you.
Doug
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This is a service manual in every sense of the word ( French and German versions of the text are included, as well as English..)
There are explanations of the mechanical and electrical functions, plenty of mechanical drawings, and the needed schematics. The quality of the scanning is excellent - all the component values are clearly legible - and very usefully there are pcb component layouts, so you can find a component on the schematic, and then very quicky pinpoint its physical location on the relevant pcb.
I cannot see how I can give this manual any less than the maximum 5 stars! Great value for money, which will pay for itself immediately. Excellent all round!
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the manual is great and especially hard to find... thanks for the great service and having a hard to find manuel_
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8575 N/B Maintenance
Two separate buses, Host-t-GUI in the width of 64 bit, and GUI-t-Memory Controller in the width of 128 bit are devised to ensure concurrency of Host-t-GUI streaming, and GUI-t-MC streaming. In PC133, or DDR266 memory subsystem, the 128 bit GUI-t-MC bus will attain the AGP4X or AGP 8X equivalent texture transfer rate, respectively. The Memory Controller mainly comprises the Memory Arbiter, the M-data/MCommand Queues, and the Memory Interface. The Memory Arbiter arbitrates a plenty of memory access requests from the GUI or AGP controller, Host Controller, and I/O bus masters based on a default optimized priority list with the capability of dynamically prioritizing the I/O bus master requests in a bid to offering privileged service to 1) the isochronous downstream transfer to guarantee the min. latency & timely delivery, or 2) the PCI master upstream transfer to curb the latency within the maximum tolerant period of 10us. Prior to the memory access requests pushed into the M-data queue, any command compliant to the paging mechanism is generated and pushed into the M-CMD queue. The M-data/M-CMD Queues further orders and forwards these queuing requests to the Memory Interface in an effort to utilizing the memory bandwidth to its utmost by scheduling the command requests in the background when the data requests streamlines in the foreground.
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