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There are currently no product reviews.
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Good quality, clear diagrams. Exactly what I needed.
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Good product. All the information is invcluded, but due to the complexity of the amplifier, it still is difficult to get it to operation again.
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Very professional seller; very fast, accurate and rielable service.
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great works fine, got the manual on mail within a day
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First class Service,
best quality, come again
Thank You.
vac
Pin No. 39 40 41 42 43 44 45 46 47 48 49 50
Pin Name DA11 DA10 DA09 DA08 DA07 DA06 DA05 DA04 DA03 DA02 DA01 APTR
I/O O O O O O O O O O O O O
Description DA11 output when PSSL=1. GTOP output when PSSL=0. DA10 output when PSSL=1. XUGF output when PSSL=0. DA09 output when PSSL=1. XPLCK output when PSSL=0. DA08 output when PSSL=1. GFS output when PSSL=0. DA07 output when PSSL=1. RFCK output when PSSL=0. DA06 output when PSSL=1. C2PO output when PSSL=0. DA05 output when PSSL=1. XRAOF output when PSSL=0. DA04 output when PSSL=1. MNT3 output when PSSL=0. DA03 output when PSSL=1. MNT2 output when PSSL=0. DA02 output when PSSL=1. MNT1 output when PSSL=0. DA01 output when PSSL=1. MNT0 output when PSSL=0. Aperture compensation control output. This pin outputs a high signal when the right channel is used.
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76
APTL VSS XTAI XTAO XTSL FSTT FSOF C16M MD2 DOUT EMPH WFCK SCOR SBSO EXCK SQSO SQCK MUTE SENS XRST DATA XLAT VDD CLOK SEIN CNIN
O � I O I O O O I O O I O O I O I I � I O O
Aperture compensation control output. This pin outputs a high signal when the left channel is used. GND. Crystal oscillation circuit input. Crystal oscillation circuit output. Crystal selector input. 2/3 frequency divider output for Pins 53 and 54. 1/4 frequency divider output for Pins 53 and 54. 16.9344MHz output. (V16M output in CLV-W and CAV-W modes) Digital-out on/off control. High: on; low: off Digital-out output. Outputs a high signal when the playback disc has emphasis, and a low signal when there is no emphasis. WFCK (write frame clock) output. Outputs a high signal when either subcode sync S0 or S1 is detected. Sub P to W serial output. SBSO readout clock input. Sub Q 80-bit and PCM peak, level metter and internal status outputs. SQSO readout clock input. High: mute; low: release SENS output to CPU. System reset. Reset when low. Serial data input from CPU. Latch input from CPU. Serial data is latched at the falling edge. Power supply (5V).
O I I
Serial data transfer clock input from CPU. SENS input from SSP. Track jump count signal input.
21
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