SONY CMH888RC
Service Manual

2-2-3. Transmitter Circuit The modulator generates transmit signal with VCO and to fed the discrete switch circuit. The output signal of the discrete switch circuit is fed to the power amplifier (U402). The output signal of the power amplifier is fed to the directional coupler (U401) and then the duplexer filter (FL401). A sample of the RF output power is coupled off, and passed through the detector (CR401) and fed to the logic circuit for APC loop. The p-cont signal from the logic circuit controls power amplifier level controllers (Q403, Q405) to control the power amplifier (U402) output level. 2-2-4. Receiver Circuit The receiver is a double conversion super-heterodyne receiver, capable of receiving frequencies from 869 MHz to 894 MHz. The RX signal from duplexer filter (FL401) is amplified by LNA (Q301) with band-pass filter (FL301) and fed to the double balanced mixer (U301). The synthesizer output signal is also fed to the mixer to obtain the first IF signal (72.06 MHz). The first IF signal is fed to the second mixer through first amplifier (Q303) and x�tal filter (FL302) and then heterodyned with a fixed 72 MHz second local VCO signal obtain a 60 kHz second IF signal. The second local oscillator signal is produce by signal synthesizer (U304) and discrete VCO. After this frequency conversion, the signal second IF fed to the monolithic low-power IF system (U302) incorporating two limiting IF amplifiers quadrature detector, logarithmic signal strength indication (RSSI) and voltage regulator. The detected output signal and RSSI signal are fed to the logic circuit.

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