AIWA CSDA660
Service Manual

Pin No.
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

Pin Name
HFL SLOF CV�

I/O
O the pit or on the mirror. I I Sled servo off control input. CLV error signal input from the DSP. RF output.

Description
The HFL (high frequency level) signal is used to judge whether the main beam is positioned on

CV+ RFSM RFS� SLC SL1 DGND FSC TBC NC DEF CLK CL DAT CE DRF FSS VCC2 REF1 VR LF2 PH1 BH1 LDD LDS VCC1 O O O waveform. I � O I � O I I I I O I respect to the reference voltage). (Not used) � _ O � � � O I � VCC of servo and digital circuits. For the connection of bypass capacitor for the reference voltage. Reference voltage output. Sets the time constant for disc defect detection. For the connection of a capacitor to hold the RF signal peak. For the connection of a capacitor to hold the RF signal bottom. APC circuit output. APC circuit input. VCC of RF signal circuits. Input to control the DSP's data slice level. Ground of digital signals. Output for the focus search smoothing capacitor. The TBC (tracking balance control) signal sets the EF balance variation range. Not connected. Disc defect detection output. Reference clock input. 4.23 MHz is input from the DSP. Microprocessor command clock input. Microprocessor command data input. Microprocessor chip enable input. DRF (detect RF) is an output to detect the RF level. The FSS (focus search select) signal switches the focus search modes (+/-search / +search with

Sets the RF gain and the EFM signal's 3T compensation constant together with the RFSM pin. The SLC (slice level control) signal is output to control the DSP's data slice level of the RF

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