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HCD-X1
MIB01 BOARD IC506 ADV7300AKST (VIDEO ENCODER) Pin No. 1 2 to 9 10 11 12, 13 14 to 18 19 20 21 22 23 24 25 26 to 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51, 52 53 to 55 56 57 58 to 62 63 64 Pin Name VDD_IO
P_Y (0) to P_Y (7)
I/O I I I I/O I I I I I I I I I O O O O O O I I I I I I I I Power supply terminal (+3.3V)
Description Video signal input from the progressive scan converter Power supply terminal (+2.5V) Ground terminal Video signal input from the progressive scan converter Video signal input from the progressive scan converter Not used Not used Two-way data bus with the servo DSP Serial data transfer clock signal input from the servo DSP Horizontal sync signal input terminal Not used Vertical sync signal input terminal Not used Blanking signal input terminal Not used Video signal input from the progressive scan converter Not used System clock input (27 MHz) from the progressive scan converter System reset signal input from the servo DSP "L": reset Connected to the external loop filter Component video signal output level adjustment signal terminal Not used Video signal (red) output to the video amplifier Video signal (blue) output to the video amplifier Video signal (green) output to the video amplifier Ground terminal Power supply terminal (+2.5V) Chroma video signal output to the video amplifier Luma video signal output to the video amplifier CVBS video signal output to the video amplifier Not used Not used Composite video signal output level adjustment signal terminal Blanking signal input terminal Not used Vertical sync signal input terminal Not used Horizontal sync signal input terminal Not used Video signal input terminal Not used Video signal input from the progressive scan converter Power supply terminal (+2.5V) Ground terminal Video signal input from the progressive scan converter System clock input (27 MHz) from the progressive scan converter Ground terminal
VDD GND
P_Y (8), P_Y (9) P_C (0) to P_C (4)
SPI_II2_EN ALS8 SDA SCL P_HSYNC P_VSYNC P_BLANK
P_C (5) to P_C (9)
RTC/SCRESET/TR
CLKIN RESET EXT_LF RSET2 COMP2 CR/B CB/R Y/G GND VAA C Y V COMP1 VREF RSET1 S_BLANK S_VSYNC S_HSYNC S (0), S (1) S (2) to S (4) VDD GND S (5) to S (9) CLKIN_2 GND_IO
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