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HT-R340 IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS-4
Q201 : ADSP-21266(32 bit, Floating-point SHARC DSP)-4/5
TERMINAL DESCRIPTION(3/3)
Pin CLKIN Type I Function Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-21266 clock input. It configures the ADSP-21266 to use either its internal clock generator or an external clock source. Connecting the necessary components to CLKIN and XTAL enables the internal clock generator. Connecting the external clock to CLKIN while leaving XTAL unconnected configures the ADSP-21266 to use the external clock source such as an external clock oscillator. The core is clocked either by the PLL output or this clock input depending on the CLKCFG1�0 pin settings. CLKIN may not be halted, changed, or operated below the specified frequency. Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external crystal. Core/CLKIN Ratio Control. These pins set the start up clock frequency. See Table 6 for a description of the clock configuration modes. Note that the operating frequency can be changed by programming the PLL multiplier and divider in the PMCTL register at any time after the core comes out of reset. Reset Out/Local Clock Out. Drives out the core reset signal to an external device. CLKOUT can also be configured as a reset out pin (RSTOUT). The functionality can be switched between the PLL output clock and reset out by setting Bit 12 of the PMCTL register. The default is reset out. Processor Reset. Resets the ADSP-21266 to a known state. Upon deassertion, there is a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins program execution from the hardware reset vector address. The RESET input must be asserted (low) at power-up. Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted (pulsed low) after power-up or held low for proper operation of the ADSP-21266. Test Mode Select (JTAG). Used to control the test state machine. TMS has a 22.5 k ohms internal pull-up resistor. Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 22.5 k ohms internal pull-up resistor. Test Data Output (JTAG). Serial scan output of the boundary scan path. Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-up or held low for proper operation of the ADSP-21266. TRST has a 22.5 k ohms internal pull-up resistor. Emulation Status. Must be connected to the ADSP-21266 Analog Devices DSP Tools product line of JTAG emulators target board connector only. EMU has a 22.5 k ohms internal pull-up resistor. Core Power Supply. Nominally +1.2 V dc and supplies the DSP�s core processor (13 pins on the BGA package, 32 pins on the LQFP package). I/O Power Supply. Nominally +3.3 V dc (6 pins on the BGA package, 10 pins on the LQFP package). Analog Power Supply. Nominally +1.2 V dc and supplies the DSP�s internal PLL (clock generator). This pin has the same specifications as VDDINT, except that added filtering circuitry is required. For more information, see Power Supplies on Page 8. Analog Power Supply Return. Power Supply Return. (54 pins on the BGA package, 39 pins on the LQFP package).
XTAL
O
CLKCFG1�0 I
RSTOUT/ CLKOUT
O
RESET
I/A
TCK TMS TDI TDO TRST EMU VDDINT
I I/S I/S O I/A O (O/D) P
VDDEXT AVDD
P P
AVSS GND
G G
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