|
|
|
Categories
|
|
Information
|
|
Featured Product
|
|
|
 |
|
|
There are currently no product reviews.
 ;
It was helpful to get schematic with waveforms in important points and lot of service information. Manual is good quality, fast delivered. Of course it is hardcopy of paper one with all its disadvantages.
 ;
I want to give you a real heads-up for your desire to enable such people as I to acquire the information I need to maintain the older types of equipment such as this Akai HXA351W. You do a swell job with all the processes you have to perform so I can have a legible, thus usable
document which does not send me crazy trying to figure out the blurry text of a bad copy.
Very well done, Thomas.
 ;
This manual is very well presented and after printing out looks about as close to an original as I think you can get. The quality is second to none.
The content of the manual is comprehensive and I think it would be well suited to an audio repair professional which I'm not but I did find it very informative and helpful.
The cost of the manual is more than covered by the money I'll save when I change the keep memory battery now I have the relavant info.
Very pleased with my purchase and can recommend it wholeheartedly as I can other manuals I've downloaded from this site.
Regards
Limey Alex
 ;
Complete manual including mechanical part in good pdf quality. Shaded greys of the pcb due to pdf not perfect but usable.
 ;
Nice pdf file of the manual sent promptly. Thanks.
8)
Gate array
GND
When VDD is applied from power supply IC SC371015FU to gate array µPD65005GC-556Open (Pin 26) (Pin 25) MON
3B6, gate array will send "L" signal to active the main switch signal from terminal SWO. Also, gate array will send "H" signal to release the INT0 terminal of CPU from LSO terminal. The terminal CSB is for the chip select of gate array. This signal is sent from CPU terminal CS2. And when the VDD is applied to CPU, CPU will send "H" signal to CSB terminal.
"L"
TO MAIN SWITCH (Pin 40) SWO
LSI GATE ARRAY
µPD65005GC-566-3B6
"H" TO CPU INT0 terminal (Pin 70) (Pin 27) LSO (Pin 7) (Pin 33)
(Pin 34)
VDD
GND
CSB (Pin 24) "H" FROM CPU CS2 terminal (Pin 28)
9)
Main switch and power on switch
VDD
MAIN SWITCH (Pin36) SW "L" OFF ON (Pin40) "L"
GATE ARRAY
SWO
CPU
HD62076C02
µPD65005GC-566-3B6
KAC (Pin54) "L"
KIO (Pin53) "H"
POWER ON SWITCH
When the main switch is set to on position, SW terminal of CPU becomes "L", then CPU will send "L" signal to KAC terminal to enable the system power on. The KI0 terminal is "H" when VDD is applied to CPU. Therefore, when pressing the power on switch, CPU will generate a clock pulse (2 MHz) for start up the system.
� 19 �
|
|
 |
> |
|