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Fully functional usable service manual. Considering the age of the manual and device quality was better than expected
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Thank you very much, I've been very happy to find this manual on "Owner Manual". It's a perfect copy and it has been really useful for my work!
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It took about 24-hours after my payment before I was able to get to the download. Apparently, payment processing is not 100% automated. That is no big deal, just be aware of that going in.
After I got to it, it was in good shape, easy to read, etc. Not some cheap FAX copy looking thing.
Also, this site was the cheapest I found. Another Plus!
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Good price, very legible manual, exactly what I needed -- but had to wait a day to actually get the download of the manual. Would have preferred to download it immediately after payment rather than waiting for someone to "process" my order. I was surprised that I had to wait that long.
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As the only source for this manual it rather rank quite high since it is well scanned and perfectly readable.
MD-P100
- Pin Functions(CXD2535CR-1)
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Pin Name FS256 FOK DFCT SHCK SHCKEN WRPWR DIRC SWDT SCLK XLAT SRDT SENS ADSY SQSY DQSY xrst TEST4 CLVSCK TEST5 DOUT DIN FMCK ater REC DVSS DOVF DODT DIDT DTI DTO C2PO BCK LRCK XTAO XTAI MCLK XBCK DVDDO WDCK RFCK WFCK GTOP gfs XPLCK I/O O O O O I I I I I I O O O O O I I O I O I O O I Function and Operation 11.2896MHz clock signal output (MCLK system) Not used this set (OPEN) Focus OK signal output to the system controller (IC600) �H� is output when the focus is applied Defect ON/OFF selection signal output to CXD2536CR (IC500) Track jump detection signal output to the system controller Not used this set (OPEN) Track jump detection enable input Not used this set (Fixed at �L�) Laser power selection signal input from the system controller Not used this set (Fixed at �L�) Not used this set (Fixed at �H�) Write data signal input from the system controller (IC600) Serial clock signal input from the system controller (IC600) Serial latch signal input from the system controller (IC600) Read data signal output to the system controller (IC600) Internal status (SENS) output to the system controller (IC600) ADIP sync signal output Not used this set (OPEN) Sub-code Q sync (SCOR) output to the system controller (IC600) �L� every 13.3msec,Almost �H� Digital in U-bit CD format sub-code Q sync (SCOR) output to the system controller (IC600) �L� every 13.3msec,Almost �H� Reset signal input from the system controller (IC600) When reset �L� Test input terminal (Fixed at �L�) Not used this set (OPEN) Test input terminal (Fixed at �L�) Output terminal of the digital audio signal (for optical out) Not used this set (OPEN) Input terminal of the digital audio signal (for optical out) Not used this set (Fixed at �L�) FM modulation clock signal output of the ADIP Not used this set (OPEN) ADIP CRC flag output When error �H� Not used this set (OPEN) Record/playback selection signal input When recording :�H�, when playback:�L� (Fixed at �L�) Ground terminal (Digital system) Validity flag input terminal for the digital audio out Not used this set (Fixed at �L�) Input terminal of 16-bit data signal for the digital audio out Not used this set (Fixed at �L�) Output terminal of 16-bit data signal for the digital audio in Not used this set (OPEN) Record audio data signal input from CXD2536CR (IC500) Playback audio data signal output to CXD2536CR (IC500) C2PO (indicate the error state of the data) signal output to CXD2536AR (IC500) Playback:C2PO (�H�), Digital recording:D.In-Vflag,Analog recording:�L� Bit clock (2.8224MHz) signal output to CXD2536CR (IC500) (MCLK system) L/R clock (44.1kHz) signal output to CXD2536CR (IC500) (MCLK system) System clock (512Fs=22.5792MHz) signal output Not used this set (OPEN) System clock (512Fs=22.5792MHz) signal input from CXD2536CR (IC500) MCLK clock (22.5792MHz) signal output Not used this set (OPEN) BCK (pin 32)inverted output Not used this set (OPEN) Power supply terminal (+3.3V) (Digital system) WDCK clock (88.2kHz) signal output (MCLK system) Not used this set (OPEN) RFCK clock (7.35kHz) signal output (MCLK system) Not used this set (OPEN) WFCK clock (7.35kHz) signal output (When playback:EFM decoder PLL system, When recoding:EFM encoder PLL system) Not used this set (OPEN) Opens the playback EFM frame sync protection window when �H� Not used set (OPEN) The playback EFM frame sync and interpolation protection timing match when �H� Not used this set (OPEN) EFM decoder PLL clock (98Fs=4.3218MHz) signal output Falling edge of the EFM PLL clock and the EFM signal match Not used this set (OPEN)
I I O I O O O O O I O O O O O O O O
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