TOSHIBA SD-240ESR
Circuit Diagrams

Q802 STR-A6351
3 Vin

+ -

REG Latch Delay

REG PUM Latch S& R OCP Comp.
+

OSC

Drive 1 S OCP/FB

lcont

U8 BA4558F

U2, U7 TL3742CD
1OUT 1 2 3 8 7 6 VCC+ 2OUT 2IN-

OUT1 1

8 VCC

IN1

2

1ch
+

7 OUT2 2ch

+IN1 3

+

6

IN2

VEE 4

5 +IN2

U12 SST39V800FA
EEPROM Cell Array

X-Decoder

Memory Address Address Buffer & Latches Y-Decoder

CE# OE# WE#

Control Logic

+

Internal Disk

TSD

+

UVLO

OVP

7,8 D

4

2,5 GND

1IN1IN+

VCC- / GND

4

5

2IN+

I/O Buffers and Data Latches

DQ15 - DQ0