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Good quality, all schematics of few of models. There is also short form of user manual and regulation manual.
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Perfect copy of the service manual. you can enlarge every page, and it comes up
with all details.
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It´s very very nice manual with all, what i need. Original in good quality. Very fast business. Very much thanks...
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Purchased the manual that I was looking for at a great price and could download it easily.. Great service experience and for future purchases I plan to use the site.
Thank you very much
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Exactly what was needed to assess the product - excellent value and great service
IC DESCRIPTION - 4/4 (ZR36712) - 4/4
Pin No. 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 Pin Name GPAIO[1] VCLK x 2 GND GCLK1 SCNENBL XO GCLK _________ STANDBY GND AMCLK VDD PLLGND PLLCFG[0] PLLCA PLLCFG[1] PLLVDD ICEMODE VDD ______ RESET IDLE DVDERR DVDSOS GND DVDVALID DVDSTRB DVDREQ DVDDAT0 VDD DVDDAT1 DVDDAT2 DVDDAT3 DVDDAT4 VDD DVDDAT5 DVDDAT6 DVDDAT7 GPSO GND I � I I O I � I I I I � I I I O � General purpose output, controlled by the DVP microcode (Not used) Digital ground DVD-DSP data input bus Digital power supply (3.3 V) DVD-DSP data input bus I � I � I O I/O I/O I/O � I I O I I � I/O � � I General purpose input/output pin Main video clock input or output. 27.000 MHz. Digital ground 27000 MHz clock input for audio master clock generation. In normal operation this pin must be connected directly to GND. Output to a crystal that is connected to GCLK. If a crystal is not used at GCLK, XO must be left not connected. 27,000 MHz clock or crystal input for main processing clock generation Stand-by input Digital ground Audio master clock input/output. 384, 256, 192 or 128 times the sampling frequency (programmable). Digital power supply (3.3 V) Ground plane of internal PLL circuit PLL configuration input. Allowed to be changed only during RESET. In normal operation both pins must be connected to (digital)GND. PLL capacitor. In normal operation must be connected to PLLGND through a 47nF capacitor. PLL configuration input. Allowed to be changed only during RESET. In normal operation both pins must be connected to (digital)GND. Power supply for internal PLL circuit (3.3 V) In normal operation this pin must be connected directly to VDD. Digital power supply (3.3 V) Reset input Reset, init-pclk, init-display and idle state indication output (Not used) DVD-DSP DVD-DSP start of sector input. Programmable polarity. Digital ground DVD-DSP data valid input. Programmable polarity. DVD-DSP data bit strobe (clock) input. Programmable polarity. DVD-DSP data request output. Programmable polarity. DVD-DSP data input bus Digital power supply (3.3 V) Description
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